One standard Integrated Injection Logic (IIL) memory cell, which is described as prior art in U.S. Pat. No. 4,158,237 and has a common assignee, can be implemented in a relatively small area of silicon, has relatively low power dissipation, and has speed that is acceptable in many applications. Accordingly, this memory cell has become a basic component of high density bipolar silicon memory arrays which are fabricated on a single semiconductor substrate.
The standard IIL memory cell includes a flip-flop circuit comprising two vertical n-p-n transistors with the base of each connected to the collector of the other, and two load-injectors comprising lateral p-n-p transistors with the collector of each being connected to the collector on a separate one of the n-p-n transistors. The emitters of the p-n-p transistors are coupled to first and second bit lines, respectively. A word line is coupled to the bases of the p-n-p transistors. The p-type collector region of one p-n-p transistor also serves as the p-type base of one n-p-n transistor and the n-type bases of the p-n-p transistors and the n-type emitters of the n-p-n transistors are one common region.
The standard IIL memory cell has been found to have a number of problems. Stability, the ability to retain stored information, is one problem. An alpha particle hitting the memory cell can cause the base of the conducting transistor of the flip-flop to quickly drop in potential and thereby cause the other flip-flop transistor to start conducting. This causes a loss of correct stored information. The p-n-p transistor which supplies base current to the flip-flop transistor that is supposed to be conducting is unable to rapidly supply additional base current. This is because it is operating in saturation and as such is a relatively slow responding current source which is not capable of timely restoring the alpha particle caused lost potential. The physical structure of the memory cell dictates the electrical configuration which causes the p-n-p transistor to operate in saturation. Because the emitters of the n-p-n transistors are physically the same semiconductor region as the bases of the p-n-p's, the p-n-p's are forced to selectively operate in saturation during times at which one or the other is needed to act as a fast responding current source to prevent an alpha particle from causing a loss of correct stored information.
One possible solution to this alpha particle caused stability problem is to increase the forward current gain (beta) of the p-n-p transistors so as to enhance response time such that they act as faster responding current sources. This also improves memory access time. One disadvantage of increasing the forward current gain is that it also typically increases the reverse current gain and thereby increases leakage (back injection) into the bit lines through the saturated p-n-p transistors. This can become a serious problem when there is a large array of memory cells with most storing one bit of information and only one or just a few cells storing the opposite bit of information. The leakage onto a bit line causes that bit line to rise in potential which can result in information stored in some cells being lost. Accordingly, increasing the beta of the p-n-p's can cause additional stability problems.
The operation of a standard IIL memory cell of an array of cells is quasi static in that when a cell of a selected row of the array is accessed the cells of all other rows have no dc current flow. These other cells retain the stored information as the potentials on the parasitic capacitance associated with the collectors of the n-p-n transistors. The time period during access (the read out of information or the writing in of information) must be limited or some of the nonaccessed memory cells may lose the stored information. There is essentially always some loss of the potential on the collectors of the non-accessed row n-p-n transistors and, therefore, a standby operation is required between subsequent accesses. The standby operation essentially resets the diminished potentials to their full levels and re-establishes a relatively low dc current flow through all memory cells. During standby operation the memory cells are particularly susceptible to a loss of current stored information if hit by an alpha particle because the low current level is relatively easily cut off.
Still another problem of the standard IIL memory cell is that a relatively poor trade off between obtaining larger readout currents and increasing power dissipation exists because a p-n-p transistor operating in saturation tends to have a decreasing forward beta with increasing current flow.
Still another problem with standard IIL memory cells is that back injection through one of the p-n-p's of each cell of a column of cells onto a bit line causes a bit line offset (voltage change). Only a limited change in one bit line voltage versus another bit line voltage can be tolerated before correct stored information is lost. Accordingly, the number of cells per column must be limited to maintain reasonable stability. The bit line offset also causes access time to be increased.
Still another problem of the standard IIL memory cell is that access time is slowed during a read operation because initially the bit lines see essentially equal current flow becuase the emitter-base junctions of both p-n-p's are conducting equally. Not until one of the p-n-p's starts conducting large collector-emitter current is a differential current signal developed on the bit line.
U.S. Pat. No. 4,158,237 teaches and claims an improved storage cell which contains two standard IIL structures which are formed in a single semiconductor body and are electrically isolated from each other. Each IIL structure consists of a lateral p-n-p transistor merged with a vertical n-p-n transistor with the n type base of the p-n-p transistor also serving as the n type emitter of the n-p-n transistor. This allows the emitters of the n-p-n transistors to be split apart and to be coupled to right and left bit lines. The base of each of the load-injector transistors is still coupled to one of the emitters of the n-p-n transistors. This improved cell does provide a strong read out signal at high speeds with a minimum of addressing lines, but still has the stability problems associated with the standard IIL memory cell. The reason for the stability problem is that the p-n-p transistors are forced to operate in saturation during critical operating times because of the common n-type region used for the base of the p-n-p and the emitter of the n-p-n.
It is desirable in many applications to have a bipolar memory cell which is of suitable physical size for use in high density memory arrays and which has better stability and a better tradeoff between readout current and power dissipation than the standard IIL memory cell. Additionally, it is desirable in some applications to have significantly less bit line offset and faster access than the standard IIL memory cell.